[ The PC Guide | Systems and Components Reference Guide | The Processor | Processor Architecture and Operation | Internal Processor Interfaces and Operation | Processor Instruction Sets ] Instruction Set Complexity: CISC vs. RISC The primary objective of processor designers is to improve performance. Performance is defined as the amount of work that the processor can do in a given period of time. Different instructions perform different amounts of work. To increase performance, you can either have the processor execute instructions in less time, or make each instruction it executes do more work. Increasing performance by executing instructions in less time means increasing the clock speed of the processor. Making it do more work with each instruction means increasing the power and complexity of each instruction. Ideally you'd like to do both, of course, but it is a design tradeoff; it is hard to make more complex instructions run faster. A real-life analogy would be to imagine you are pedaling a bicycle. To get where you are going more quickly, you can either use a low gear and pedal very quickly, or use a high gear and push harder. You can try to push both harder and faster, but you can never pedal as fast with a high gear as you can with a low one. This tradeoff in basic instruction set design philosophy is reflected in the two main labels given to instruction sets. CISC stands for complex instruction set computer and is the name given to processors that use a large number of complicated instructions, to try to do more work with each one. RISC stands for reduced instruction set computer and is the generic name given to processors that use a small number of simple instructions, to try to do less work with each instruction but execute them much faster. The question of which of these two approaches to use in designing a processor has become one of the great arguments of the computer world. This is especially true because once a platform makes an instruction set decision, it tends to stick with it in order to ensure compatibility with existing software. Somewhat ironically, the line between RISC and CISC has become blurred in recent years, with each moving toward the middle ground in an attempt to improve performance. In addition, new ways to mixing RISC and CISC concepts have emerged through the use of translating processors.
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