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x86 Emulation and Translation

The desire to improve performance while retaining compatibility with existing software has led processor engineers to make some very creative designs. Perhaps the most innovative design has been the complete reworking of the inner core of the processor that has been done on several of the more recent processors. This includes the Intel Pentium Pro and Pentium II, and the AMD K5 and K6.

In the section that discusses CISC and RISC processors, I alluded to the fact that the two have become less distinct in recent years. These latest processors do more than blur the line between the two, they really use both! The internal execution core of this type of CPU is actually a "machine within the machine", that functions internally as a RISC processor but externally like a CISC processor. The way this works is explained in more detail in other sections in this area, but in a nutshell, it does this by translating (on the fly, in hardware) the CISC instructions into one or more RISC instructions. It then processes these using multiple RISC execution units inside the processor core.

This design has been created to allow PC processors to reap the benefits of RISC instruction sets while maintaining compatibility with existing x86 code. The internal RISC core is more suited to implementing many of the more advanced performance-enhancing architectural features, as well as being easier to run at much higher clock speeds. Faster clock speeds mean less time to perform each instruction, and therefore it makes sense to chop the large, complicated CISC x86 instructions into more "digestible" pieces to gain performance as clock speeds exceed 200 MHz. From the user's perspective, this additional layer of translation is totally invisible, since it happens entirely within the processor itself.

The x86 translation scheme is discussed in more detail here.

Next: IA-64: The End of x86?

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