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Bus Bandwidth

Bandwidth, also called throughput, refers to the total amount of data that can theoretically be transferred on the bus in a given unit of time. Using the highway analogy, if the bus width is the number of lanes, and the bus speed is how fast the cars are driving, then the bandwidth is the product of these two and reflects the amount of traffic that the channel can convey per second.

The table below shows the theoretical bandwidth of most of the common I/O buses on PCs today. Note the italics on the word "theoretical"; most buses can't actually transmit anywhere near these maximum numbers because of command overhead and other factors. This is especially true of older buses. For example, the theoretical bandwidth of the 8-bit ISA bus might be about  MBytes/sec, but in reality there are wait states inserted during I/O that drop this figure down dramatically.

Most of these buses can run at many different speeds; the speed listed is the one most commonly used for the bus type. See here for a similar table showing processor and memory bus bandwidth for various processors.

Note: You may be somewhat confused by the bandwidth numbers I have listed in the table above. For example, shouldn't the bandwidth of standard PCI be 32/8*33.3=133.3 MB/sec? This is how most people and even companies write it, but this is not technically correct, because of the old problem of different definitions of what "M" stands for. The "M" in "MHz" is 1,000,000 (10^6), but the "M" in "MBytes/second" is 1,048,576 (2^20). So the bandwidth of the PCI bus is more properly stated as 32/8*33.3*1,000,000/1,048,576=127.2 MBytes/second.

A few words on the last four entries. In theory, the PCI bus can be extended to 64 bits in width, and 66 MHz in speed. However (here it comes again) for compatibility reasons almost all PCI buses and the devices they run in, are rated for only 33 MHz at 32 bits. AGP is based upon this theoretical standard and does run at 66 MHz, but remains only 32 bits wide. AGP has additional modes, dubbed x2 and x4, that allow the port to perform data transfers two or four times per clock cycle, respectively, leading to an effective bus speed of 133 or 266 MHz.

Next: Bus Interfacing

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