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DRAM Write Timing / DRAM Burst Write Timing / DRAM Write Wait States

This parameter controls how many clock cycles are required for the burst writes to memory during a four-read "burst". In most modern PCs, writes to the system memory are done in sets of four, because the level 2 cache used in the PC (which is filled by information from the main memory) is 256 bits wide (four sets of 64 bits). The timing, in clock cycles, to perform this quadruple write is normally stated as "x-y-y-y". The first write is slower because the address for the write must be supplied to the memory; the next three are faster because they are written consecutively to the addresses immediately following the first location (no need to supply an address). Memory system timing is discussed in much more detail here.

Using the x-y-y-y notation, the Write Timing or Burst Write Timing setting refers to the "y-y-y" value, the number of clock cycles for the 2nd, 3rd and 4th writes of the four-write cycle. This setting will most often have options like "x-2-2-2", "x-3-3-3" and "x-4-4-4", although in some BIOSes the single number is used instead ("2", "3", "4".) Some BIOSes, especially on older machines, instead refer to write "wait states", which is essentially the same thing, except that it is one less than the number referred to above. A wait state is an extra cycle inserted for the processor to wait for the system memory. In the x-y-y-y notation, the "y" is the total number of cycles. "x-1-1-1" is the best you can do, since it always takes at least one cycle. Zero wait states is the best you can do. So "x-3-3-3" is equivalent to 2 wait states.

Note: Systems that have a double value for read burst timing (one for EDO memory and one for FPM) will still have just a single value for write burst timing. This is because EDO is only faster than FPM memory when reading.

Your system will operate fastest when this setting is as low as possible. How low you can set this depends on your memory bus speed and the speed and type of memory you are using. In general, the faster your memory bus runs the more cycles it will take to access the memory unless the memory is also made faster. Putting this setting too low will cause memory errors; some of these can appear intermittently and be very difficult to diagnose. Using automatic timing to set this parameter is usually recommended. By default most BIOSes enable automatic timing settings so this parameter would be "locked out" and not changeable; if you enable manual timing settings this setting will usually default to the slowest possible setting at first, for compatibility reasons.

Note: This setting is normally controlled by the DRAM Timing or Auto Configuration mode, and if automatic settings are enabled you may not be able to change this.

Note: On some BIOSes this setting is combined with DRAM Read Timing / DRAM Read Burst Timing. In this case the same timing is used for both reads and writes.

Next: DRAM Speculative Leadoff

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