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Cache Timing

This setting determines the speed that the chipset will use for reading data from the external (level 2) cache. This normally appears as something like x-y-y-y. In this case the parameter refers to the number of clock cycles to do a 32-byte burst read from the external cache line. Each entry in the cache of a modern PC is 256 bits wide; data is read from the cache using four consecutive 64-bit reads. The first read is normally slower than the others; this is the "x" above, and the next three reads are the "y"s. An example would be "3-1-1-1", which means it takes a total of six clock cycles to read from the cache. More information on cache timing can be found here.

In general, the lower these numbers, the faster your system will be. How low you can drop them depends on your system, how fast your memory is, what clock speed your memory bus runs at, etc. If your BIOS supports an "Auto" setting for this parameter, using it is normally wisest, although it may not produce the highest performance results. You can try more aggressive settings (lower numbers) but be prepared to back off if you experience system problems, and don't go below the rating for your cache type.

Next: Level 2 Cacheable DRAM Size / Cache Over 64 MB of DRAM

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